ADT7473
45.52 ms, Bit 1 of the THERM timer is set and Bit 0
becomes the LSB of the timer with a resolution of 22.76 ms
(see Figure 32).
When using the THERM timer, be aware of the following.
After a THERM timer read (0x79):
1. The contents of the timer are cleared on read.
2. The F4P bit (Bit 5) of Interrupt Status Register 2
needs to be cleared (assuming that the THERM
timer limit has been exceeded).
If the THERM timer is read during a THERM assertion,
then the following happens:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM timer is set to 1 (because a
THERM assertion is occurring).
3. The THERM timer increments from 0.
4. If the THERM timer limit (Register 0x7A) = 0x00,
the F4P bit is set.
THERM
THERM timer events. Register 0x7A is the THERM timer
limit register. This 8-bit register allows a limit from 0 sec
(first THERM assertion) to 5.825 sec to be set before an
SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit
register. If the THERM timer value exceeds the THERM
timer limit value, the F4P bit (Bit 5) of Interrupt Status
Register 2 is set and an SMBALERT is generated. The F4P
bit (Bit 5) of Interrupt Mask Register 2 (0x75) masks out the
SMBALERT if this bit is set to 1; however, the F4P bit of
Interrupt Status Register 2 still is set if the THERM timer
limit is exceeded.
Figure 33 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes an
SMBALERT to be generated on the first THERM assertion.
A THERM timer limit value of 0x01 generates an
SMBALERT once cumulative THERM assertions exceed
45.52 ms.
Configuring the THERM Behavior
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
? 22.76 ms
1. Configure Pin 9 as a THERM timer input. Setting
Bit 1 (THERM timer enable) of Configuration
Register 3 (0x78) enables the THERM timer
monitoring functionality. This is disabled on Pin 9
by default. Setting Bit 0 and Bit 1 (PIN9FUNC) of
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
Configuration Register 4 (0x7D) enables THERM
timer/output functionality on Pin 9 (Bit 1 of
Configuration Register 3, THERM, must also be
set). Pin 9 can also be used as TACH4. Setting
Bit 5, Bit 6, and Bit 7 of Configuration Register 5
(0x7C) makes THERM bidirectional. This means
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
? 45.52 ms
that if the appropriate temperature channel exceeds
the THERM temperature limit, the THERM output
asserts. If the ADT7473 is not pulling THERM low,
but THERM is pulled low by an external device
(such as a CPU overtemperature signal), the
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM timer also times THERM assertions. If
Bit 5, Bit 6, and Bit 7 of Configuration Register 5
(0x7C) are set to 0, THERM is set as a timer input
only.
2. Select the desired fan behavior for THERM timer
events. Assuming the fans are running, setting
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
? 113.8 ms
(91.04 ms + 22.76 ms)
Bit 2 (BOOST) of Configuration Register 3 (0x78)
causes all fans to run at 100% duty cycle whenever
THERM is asserted. This allows fail-safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If
Figure 32. Understanding the THERM Timer
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7473/ADT7473 ? 1 can generate an
SMBALERT when a programmable THERM timer limit is
exceeded. This allows the system designer to ignore brief,
infrequent THERM assertions, while capturing longer
the fans are not already running when THERM is
asserted, the fans do not run at full speed.
3. Select whether THERM timer events should
generate SMBALERT interrupts. Bit 5 (F4P) of
Interrupt Mask Register 2 (0x75), when set, masks
out the SMBALERT when the THERM timer limit
value is exceeded. This b it should be cleared if
SMBALERTis based on THERM events required.
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